Selva Murali is helping design the chips that power AI factories, data centers, laptops, and the connected devices shaping modern life. As a staff-level engineer at AMD, Selva works on leading-edge semiconductor technology nodes, circuit design, physical implementation, and the use of AI and machine learning to improve chip performance, power, and area.
In this episode, Russ and Selva discuss what it really takes to build faster, smaller, more power-efficient chips in an AI-driven world. Selva explains how physical design sits between architecture and circuits, why power is becoming one of the biggest bottlenecks for AI infrastructure, and why data center scale computing depends as much on heat, energy, and layout as it does on raw performance.
The conversation explores how machine learning is changing semiconductor design by running thousands of layout iterations faster than a human team could manually test. Selva explains how ML can improve timing, reduce gates, save engineering time, and help teams make better decisions with data.
Russ and Selva also discuss the differences between Samsung and AMD, the shift from mechanical to semiconductor-driven industries like automotive, the growing importance of chip packaging, and why the semiconductor field needs more young engineers willing to work at the intersection of hardware, software, and AI.
As one of BIG’s all-star judges, Selva also shares how judging innovation, cybersecurity, AI, and customer service nominations has changed the way he thinks about customers, internal teams, and the real-world impact of technology.
Topics Covered:
[00:01] Welcome and intro, Selva Murali, AMD, and BIG judging
[00:58] Selva’s work on leading-edge semiconductor nodes
[01:30] AI and ML for circuit design
[02:23] Where digital meets physical in chip design
[03:05] Front-end design versus back-end physical implementation
[04:38] Making chips faster, smaller, and more power efficient
[05:08] Explaining semiconductor design in simple terms
[05:34] How chips became part of nearly everything
[06:31] Comparing Samsung and AMD design environments
[10:10] The real AI infrastructure bottleneck
[10:34] Why power may be the biggest limit for data centers
[11:57] Heat, cooling, and data center scale
[12:20] What happens when power, performance, or area targets are missed
[13:47] Why chip layout is harder today than 10 years ago
[15:52] Foundry rules and avoiding unusable silicon
[16:27] Using machine learning to automate physical design
[16:44] Testing thousands of chip layout iterations
[19:08] How ML reduced manual work from days to minutes
[21:32] Building trust in ML-driven design with data
[22:52] Power, performance, and area tradeoffs
[23:23] Why CPUs and GPUs prioritize different design goals
[25:13] What it takes to move a chip from design to shipping
[27:00] Packaging, boards, skilled labor, and semiconductor bottlenecks
[28:52] What makes an innovation submission truly strong
[30:24] What semiconductor growth feels like inside engineering teams
[31:40] Training the next generation of chip designers
[35:51] Why students are showing more interest in circuit design
[36:46] How judging customer service changed Selva’s perspective
[39:11] Treating internal customers with more care and urgency
[40:48] Final thoughts on judging and the BIG community
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